1. Technical Field
Example embodiments relate to semiconductor devices, and more particularly to semiconductor devices having a power gating unit and systems-on-chip including the semiconductor devices.
2. Description of the Related Art
A system-on-chip includes a power gating unit, which is turned on or turned off according to operation modes, for reducing power consumption. Generally, the power gating unit includes a logic block and a switch that controls a flow of current from a supply voltage to a ground voltage through the logic block. The switch is turned on in a normal mode to operate the logic block by passing the current through the logic block and is turned off in a standby mode to block the current for reducing power consumption.
If the switch is turned off, an output signal of the power gating unit is floated. That is, a logic level of the output signal of the power gating unit is not determined as a logic low level or a logic high level.
Conventionally, an isolation cell is inserted between the power gating unit and the combinational logic unit to provide a signal having a predetermined logic level to the combinational logic unit even if the power gating unit is turned off. However, an operation speed of the system-on-chip having the isolation cell is slowed since a signal is delayed by an insertion of the isolation cell.